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Andrew Zonenberg

That's it for tonight since I have to be up for work in the morning.

Next step is going to be building out more firmware and gateware around the management interface:

* Make the MDIO bus accessible over QSPI from the MCU, rather than just a JTAG debug core
* Finish the FIFO logic and interface code on both MCU and FPGA side, so I can send and receive Ethernet frames from the MCU
* Verify SSH over real Ethernet

Jul 21, 2023, 07:20 AM·Public·Web
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