@jfmezei :How long are data blocks for each entry in the in-CPU cache? 64 bits ? 128 bytes ? 1 page ?
It varies. Most implementations will use one cache block size at a time at a given cache level, but that size and the size and the organization of the caches varies.
:Does this vary from architecture to architecture or even inside an architecture?
Yes. Alpha caching varied by processor and by implementation, all within the limits of the Alpha architecture.
:Is it totally transparent when writing at OS level?
Totally transparent? No.
Details, such as what was locally called word tearing, alignment, memory timing, and memory lock processing, all get involved.
Similar requirements can arise in apps.
There are a few other wrinkles I’d prefer to not meet again, too.
Mostly transparent? Yes.
:And in multi core with coherent caches, when a core does a write to RAM, does memory controller propagate this to all other cores in case they have it cached? or does memory controller know which core has what in cache and send only relevant updates?
It depends. Most of what I’ve met will mark the cache contents as being invalid, and will await the next opportunity to wait for main memory to load the data, or to wait for a load from L3, or such. I can’t recall ever working on a cache-coherent multiprocessor that tried to reload the cache everywhere.
Alpha could load cache speculatively, or explicitly, or evict as needed.
http://bitsavers.org/pdf/dec/alpha/system_reference/Alpha_System_Reference_Manual_Version_7_1997.pdf
WP has a reasonable description, as well:
https://en.wikipedia.org/wiki/Cache_(computing)
Deeper still:
https://www.cs.swarthmore.edu/~kwebb/cs31/f18/memhierarchy/caching.html
More for amusement, figures 5 and 6 nicely show the shifting scale of the complexity of modern computer systems:
https://www.computer.org/csdl/journal/ts/2021/06/08704965/19HKUhJMVAQ
#digitalequipment #dec
#alpha #computerarchitecture #retrocomputing
