Michael Engel<p>Success on real hardware! </p><p>This is the f9 microkernel ported to RISC-V, specifically ESP32C3, by Ruben Sevaldson, a former student of mine at NTNU in 2022 – plus a small Lisp machine running on top. </p><p>Now let's see why this doesn't work in qemu for esp32c3...</p><p><a href="https://github.com/rubensseva/f9-riscv" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="">github.com/rubensseva/f9-riscv</span><span class="invisible"></span></a><br><a href="https://github.com/f9micro/f9-kernel" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="">github.com/f9micro/f9-kernel</span><span class="invisible"></span></a></p><p><a href="https://sueden.social/tags/f9" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>f9</span></a> <a href="https://sueden.social/tags/riscv" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>riscv</span></a> <a href="https://sueden.social/tags/microkernel" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>microkernel</span></a> <a href="https://sueden.social/tags/esp32c3" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>esp32c3</span></a></p>