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Bottom side substrate photo, mirrored so it lines up with the top-down view in the datasheet. Ball A1 in top left corner. Slightly overexposed on the top left but it'll do.

A few of the lands look to have small amounts of solder residue that I didn't quite clean off fully, so before I reball I'll inspect and possibly clean them up. Hard to tell exactly how much solder there is in this lighting.

There's also a scratch in the soldermask around the T-U 12-13 region. Shouldn't be a big problem but I might try to touch it up just to make sure I don't get any problems.

The substrate matches the ballout perfectly (further evidence the chip is real) although there are a few interesting things:

* The GTY refclks don't have ground plane cutouts around them for impedance matching, only the high speed SERDES

* There's a tiny single-pin ground island next to the VCCAUX_IO island. Why not just fill with VCCINT there?

* Most interestingly, the VCCO zone fills don't line up with the IO banks!