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It was reworkable at least. Which is good as I didn't have enough paste left for a second print.

The FPGA came in an absolutely ludicrous amount of packaging as is usual.

Continuing to assemble the trigger crossbar. It's a pretty packed board on the top side so going slow.

Expecting to need some rework in the top left IO area despire my best attempts to clean up the solder paste prints but whatever, nothing I can't handle.

Last few IO channels done, all of the non coaxial SMT connectors on. Still a bunch of small passives but it's getting close!

All the power stuff is done just a bit more in the bottom right corner plus the front row of SMPMs.

But time to be a dad for a bit.

Ok bedtime routine is over, board fully populated and reflowed. Time to check for problems and then stuff the PTH parts.

Initial visual inspection findings: seven bridges, all on DFNs in the top left corner due to excessive paste volume from the bad print.

The main MCU also looks a touch northwest of centered on the silkscreen. Hopefully it's just silk misalignment and the BGA is in the right spot, we'll know when I try to power it up.

Found the first mistake in the board. The SFP+ cage is slightly too far inboard and the front EMI shield fingers are pushing it up.

The module still mates fine but it's angled a tad away from the board instead of parallel.

All done and ready to start bringup!

The FPGA is getting a heatsink eventually but I'm holding off for bringup as it's hard to remove once installed. If I need to do any rework I'd rather leave it off.

Ok, first step is going to be floorplanning and cable management. There's going to be a lot of dongles and test leads involved.

The IBC is going to be on the left side, with 48V input power going to it.

I'll be making some firmware tweaks to the IBC (adding a communications interface so the main board can do remote on/off, query voltage and current and temperature, etc), so I need SWD and UART to it.

Then the main board needs the big 12V power cable to the IBC plus the control cable with I2C, output enable, and 3.3V standby.

Supervisor MCU on main board needs SWD and UART.

Main MCU needs JTAG and UART.

And then the FPGA needs JTAG.

IBC is the first thing to set up, I think. The current firmware turns on the 12V output automatically and for bringup I don't want it on immediately.

Next problem: the IBC power cable is very stiff. Fine inside an enclosure if bolted down but annoying if just taped to a bench.

And the 100mm data cable is a bit short as a result ordering some 150 and 300 to get more flexibility in bench layout.

Aaaand ok, bigger problem. The data cable is wired in a straight line, but the PCB assumes pin 1 on one side maps to pin of the other (not inverted, as it's wired).

Let's see if there's any way I can re-arrange the contacts in the cable as a temporary fix.

Mid term I'll spin a tiny adapter board that mirrors the pinout, and of course on the next board design I'll get it right.

Welp, lesson learned.

https://github.com/azonenberg/pcb-checklist/commit/9799c35c4195de7278accb1f8b85a39ea2c60c3d

Looking at the cable it doesn't seem like it will be too hard to remove the contacts and reinsert them. I have three and only one needs to survive the process so fingers crossed.

Crisis averted. This was actually less work than I was afraid it would be.

Progress. Supervisor MCU is alive enough to respond over SWD when powered from the IBC.

Main 12V rail (and thus everything downstream of it) is still off.

After a brief bit of confusion swapping TX and RX on the header to the FTDI (because come on, who doesn't do that the first time you bring up a board) the supervisor is talking to me on the UART.

Now to try and turn on the 12V rail, energizing the inputs to all of the DC-DCs across the board. This is the first point in the bringup where there's a nontrivial risk of magic smoke (since the 3V3_SB rail is on a super low current LDO).

Starting to bring up power rails. As usual for my recent prototypes there's a microcontroller that has all of the EN/PGOOD signals and controls all of the rail sequencing.

12V0 came up fine and measures 11.988V, perfectly normal.

The (unswitched) 5V0 analog rail came up fine, measuring 5.0371V.

The first switched rail was 1V0, measuring 0.99195V. Also fine.

1V8 is where it gets interesting. The rail comes up just fine and seems to stabilize, but PGOOD never goes high (or at least, the supervisor doesn't think it does). So it panics, thinking that there's a short on the rail, and e-stops every power rail on the board.

Welp, I measure 100 milliohms to ground from 1V8_PGOOD. Sounds like a solder defect. Time to rip the whole setup apart and find the short...

Aaand I damaged the bodge cable to the power supply in the process. And I don't have a spare.

Hopefully this little bit of plastic isn't too important and I can tape/glue it in place until the other ones I ordered arrive...

Anyway, nothing visibly shorted on the board. I guess the next step is to pull the DC-DC module and see if there's a bridge under it?

I give up. Blasted the thing with hot air for IDK how long and it's not working. Just too much thermal mass on ground planes I guess.

I'm just gonna live without PGOOD, add a fixed 5ms timer, and hope it doesn't short in the future.

Continuing down the list of rails: 1V8 measures 1.7903V.

3V3 measures 3.29110V.

FPGA and (I think) main MCU are now responsive over JTAG.

1V2 only comes up to around 500 mV so something is shorted there, will investigate later. Pretty sure that rail is only used for the gigabit Ethernet PHY so it should be an easy fix once I find the short. Assuming it's not under the DC-DC itself which is frighteningly possible considering the state of the 1V8 PGOOD.