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@whitequark Interesting.

The most complex JTAG topology I recall seeing was XC7Z with an ADIv5 TAP and a boundary scan TAP (IIRC the FPGA program/debug TAP was also the boundary scan TAP).

But there was an option to split the two via EMIO and have separate TAPs for the FPGA and ARM using FPGA GPIOs to debug the ARM, which I actually tried once.