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Andrew Zonenberg

aaaaand there it is. Expected frame length (set by writing to FETHTX.LENGTH) is 5d4, we send 5d8 bytes of data, *and those extra bytes got pushed into the fifo*.

Logic analyzer capture showing wr_en high even when tx_wr_packetlen > tx_expected_packetlen
Dec 29, 2024, 11:17 PM·Public·Web
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