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while the utility of it as a benchmark is limited, it's delightful to me that prjunnamed can synthesize a blinky in 8 ms of wall clock time
that's milliseconds, yes
@whitequark dang, that's fast
@gsuberland it does scale at least _acceptably_, too; e.g. a design that synthesizes to 5K LUTs is about 2s
@gsuberland meanwhile it takes yosys more than that to simply parse the techmap verilog, which is incredibly funny
@whitequark haha dang
sounds like you're onto something good here :D
@gsuberland many years of lessons learned, yeah
@gsuberland now of course the really cool bit would be "we plan to apply timing constraints at the start of synthesis, and begin using them there as well" but we haven't yet reached that point
@whitequark @gsuberland I would also love to see things like intelligent retiming that accounts for the entire flow, including things like floorplan or IO constraints that force some flops to be further away from each other (rather than trying to balance only the logic timing for each segment of the net).
@whitequark @gsuberland (yes I'm quite aware of how hard this sort of thing would be, but it'd be nice)
@azonenberg @gsuberland I don't really understand retiming, from an implementation perspective, enough to make any comments much less promises, but we do want at least an equivalent of `phys_opt_design` and I've been looking into how that would work
@whitequark @gsuberland Yeah that's the kind of thing I'm thinking.
Are you planning on having a usable SV frontend (i.e. at least supports enums, structs, and interfaces)?
@azonenberg @gsuberland that is table stakes for a production grade FPGA toolchain, yes
@whitequark @gsuberland FWIW vivado gained support for arrays of interfaces late enough in the game that I had to do a major ASIC project using a bunch of structs instead of interfaces, where interfaces would have been a better fit.
DC was fine with interfaces at the time, but we needed to be able to synthesize the RTL for U+ to prototype so anything Vivado didn't support was off limits.
@azonenberg @gsuberland oh, yeah, I forgot that it had a weirdly lagging SV support for quite a while
I suppose this wouldn't really fly today, though who knows
@whitequark @gsuberland I mean I wrote all of my thesis code in v2005 because I still had a lot of Spartan-6s in the test board farm and ISE was, well, ISE.
But yeah, early vivado was missing a lot of SV features that I now use heavily. Interfaces make e.g. AMBA buses so much less painful to use. My somewhat cynical opinion is that the ip integrator exists in large part because SV support wasn't up to the point of enabling one-liner AXI connections between modules.
So rather than fixing their frontend they created a giant bloated pile of XML and slow tcl+java based code generation.