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You could totally drive SDRAM with the DQ and A pins shorted together if you were willing to give up a bit of performance, and be creative with the byte strobes and early burst termination 
@wren6991 That's a fascinating idea! I get the gist of your idea and if I get it right, you would still be able to use bursts, so it wouldn't be *that* terrible compared to what else you could get with that IO budget. Who's going to build the PoC?
@tommythorn Yes, the drawback for writes is you need an additional short burst at the end to fix up the first word, which collides with the column address. You also lose read throughput because you can't issue new read column addresses in the middle of the previous read burst. You can still get a substantial fraction of the bus throughput.
@tommythorn I keep looking at low-pin-count DRAM offerings like HyperRAM, OPI/QPI PSRAM, Etron RPC DRAM etc and they all seem to have the same problem: not enough sales volume to bring the cost-per-bit where you want it.
So turning the problem on its head, why not pick a commodity memory like LPDDR4 and ask "what's the cheapest, dumbest PHY I could build for this memory?"
@wren6991 @tommythorn meanwhile I'm continuing to dream of a low pin count serial memory I can hang off an FPGA transceiver.
Think hybrid memory cube scaled down to its bare essentials.
One TX lane, one RX lane per package. Fully independent, if you want more bandwidth you can gang two packages and get an dual channel interface using two SERDES.
The dream is RAM in an 8 pin DFN: 2x vdd, 2x vss, tx, rx.
In practice you might want to go QFN to get a few more power/ground connections and maybe a transceiver refclk but that's the goal.
@azonenberg Looking forward to seeing this overloaded onto MOSI/MISO/WPn/HOLDn on QSPI flash in the future
@wren6991 I mean I've seen RGMII and SGMII on the same IO buffers. It's plausible.
But you definitely wouldn't want to lay out a board for both... having e.g. SCK and CS# routed as a differential pair would be a nightmare if you were doing SPI mode.
@wren6991 I was thinking of this more as a hyperram replacement though.
Hyperbus: 13 pins, single ended, seems to top out at 400 MT/s on an 8 bit bus = 3.2 Gbps half duplex link bandwidth
My concept: 4 pins, differential, as fast as your SERDES IP can run, full duplex. With 16G NRZ transceivers you'd get 32 Gbps of bidirectional bandwidth for 50% read/write mix, or 10x hyperram, using 1/3 as many pins.
@azonenberg @wren6991 how much power though
@whitequark @wren6991 Probably more than hyperram.
But 32 Gbps is closer to what you'd get from a full scale SSTL bus, e.g. a 32 bit DDR3 1066 interface is 34 Gbps of interface bandwidth.
I suspect the power consumption of a single SERDES would be pretty favorable compared to 32 SSTL DQ pins, four DQS lanes, plus the C/A bus, etc. And you're doing all that with a total of four pins. There's definitely a spot in the design space it would work well for.
@whitequark @wren6991 Basically, use cases where you want a small footprint, simple board layout, and good performance but don't mind slightly higher silicon cost (you may have net system cost savings from less PCB layers routing two diffpairs instead of a full SSTL interface, and less area burned on memory routing).
@azonenberg @whitequark @wren6991 But alas this memory doesn’t exist so you’d need the equivalent of a south bridge today. I was toying with something similar (non-serdes thou) to maximize achieved bandwidth for #tinytapeout’s very meager IO budget — it’s on hold until I have an application for it.