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I'm pretty happy with the top side Samtec ARF6 launch simulations now.
S11:
* Red: No cutout, -12 dB at 10 GHz, -7 at 20 GHz, -4.8 at 30 GHz
* Blue: Rectangular ground cutout the size of the pad, -22.5 at 10 GHz, -16.4 at 20 GHz, -11.7 at 30 GHz
* Green: 30um larger than the pad on all sides (1.06 x 0.41 mm), -30.5 at 10 GHz, -22 at 20, -15 at 30.
With the oversized cutout it's more than good enough for QSGMII and 25Gbase-R.
TDR:
* Red: No cutout, 64Ω Zdiff at the launch
* Yellow: Pad-sized cutout, 86Ω
* Orange: Oversized cutout, 94Ω
@azonenberg nice! I assume you're targeting Zdiff=100Ω on this?
@gsuberland Yep.
This is the host-side launch for the connector that will be going from the FPGA board to the two line cards (two connectors, total twelve 5 Gbps NRZ lanes, per line card) as well as to the front panel dual SFP28 carrier (one connector, total four 25 Gbps NRZ lanes).
@azonenberg nice. I just noticed the trace seems to be on both sides of the pad - what's the deal with that?
@gsuberland Feedlines for the simulator, they're de-embedded but have to be present to make the ports work out.
Tl;dr you get weird results if you try to make a port that doesn't have ground on an adjacent layer to use as a reference. This is fine if you have a reference plane but if you're voiding the plane, adding a short feedline seems to usually be the easiest way to work around it.
@azonenberg ah, cool, thanks. I did wonder if it was a simulation thing. I've still not managed to get my head around EM sims, I'm hoping to get time to follow along with niconiconi's guide before too long (although I can't say I'm looking forward to battling FreeCAD). shame Sonnet is just insanely pricey.
@gsuberland Yeah.
I mean, I'm not paying MSRP though... You've heard about how I ended up getting a good deal right?
@azonenberg I vaguely recall you talking about it before but I can't remember the details.
@azonenberg lol how did that come about? worked there, or just patched it in?
@gsuberland I literally got fed up with how slow the solver was, threw it in VTune and IDA, rewrote the inner loop of their matrix solver in assembly, patched it into the binary, verified I got the same results, and got a 40-70% speedup depending on workload.
Then I sent them a "pull request".
@gsuberland After a couple days of crickets from my usually very responsive support engineer, I got an email asking me to join a call with a VP.
I figured this was gonna be really good or really bad.
@gsuberland He said he looked me up on linkedin and as soon as he saw I went to RPI (where he did his undergrad a few years before me) he knew what was going on.
Then went on to say "Sooo we've talked to our lawyers, and they say we can't have people going around breaking our EULA willy-nilly. You do realize what you did was against the terms of our license, right?"
@gsuberland "... so check your email, I've sent you an authorization on company letterhead to keep it up as long as you maintain an active support contract."
A few months later when I was visiting friends and family on the east coast, I stopped by their offices, only about a 2-hour drive from RPI where I was visiting some former classmates who had settled in the area.
Had pizza with the VP of ops I had spoken to before, their VP of engineering, my support engineer, spent several hours discussing everything from proposing improvements to the material library (having detailed Dk/Df data for specific cores and prepregs vs just an average for a given material) to looking over source code and discussing more optimization potential.
Later on I got an NDA for partial source code access, cleaned up my patch more, and upstreamed it. It just released in v19 a few weeks ago.
@azonenberg @gsuberland hahahahaha amazing
@whitequark @gsuberland I figured upstreaming would either blow up in my face or get me a really good relationship with them.
My mental calculus was that they're a tiny company (like two dozen people or so), I'm a very happy customer showing off their product all the time on my birdsite (at the time), and paying them several thousand dollars a year in support contract fees on top of the... probably around $20K? initial outlay for the seat over the years of upgrades.
And I'm offering to nearly double the speed of their product and not even asking for anything in return.
While they would be legally within their rights to sue me for breach of contract, actually doing so would be monumentally stupid.
So I decided to take the risk and tell them about it.
@azonenberg @gsuberland i don't have anything nearly as cool to report _but_ i have contributed a few patches (source and binary) against NVIDIA drivers which they either (I speculate, no formal confirmation) upstreamed, or in one case went "ok, we can't have people applying binary patches from forums with xxd, i'm going to just implement this as a proper feature"
@azonenberg @gsuberland considering that all of the things i've patched were fairly obscure (thunderbolt surprise unplug, fan control for cards used as render offload only) i count this as a win
@whitequark @azonenberg @gsuberland The culture of extensive reverse engineering and binary patching to extend proprietary dev tools on Windows has always made me smile. This is one of the crazier examples: https://gitlab.com/VC6Ultimate/VC6Ultimate
@pervognsen @whitequark @azonenberg @gsuberland TTDPatch comes to mind.
"Let's fix annoying bugs. Maybe also extend how you build things and add new UI. Then add support for bespoke gfx packs to get new train liveries. But these trains feel all the same, so maybe also add completely new drive logic. And add electrified tracks. And trams. Remove limitations on how stations can be built. Then add a fully Turing complete signals system, so that trains can actually arrive at these stations. And..."
@whitequark @gsuberland In the end they offered me something like a 40%? discount off my support contract plus to the upgrade from the level 3 gold seat I had at the time to the professional license I have now.
We had a pretty good relationship already but now I have access to early engineering builds they normally only share with like $M/yr customers, I'm on a first name basis with their head software engineer, etc.
A few months ago they emailed me asking for my advice on some stuff - not even in response to a support ticket i had opened, they were actually discussing internally how to implement some stuff and wanted to pick my brain on how to do it.
@whitequark @gsuberland But this is why I've stuck with Sonnet rather than something like HFSS.
Even if I had that kind of money, what are the odds of me ever getting this kind of relationship with Ansys?
@azonenberg @whitequark I just tested it out on a trial license and I must admit it does seem to be quite easy to set up and use. much easier than any other EM solver I've tried (well, aside from Altium, but that doesn't count)
@gsuberland @whitequark The lite tier is pretty crippling but as long as you can fit within the layer limit (and a few other things like the thick metal model) you can create arbitrarily large/complex designs in it, just not *simulate* them.
So if you have a file you want me to simulate (I can easily turn the thick metal model on for a layer if needed), it'll be super easy for me to shove it in the queue. When I'm not in crunch phase getting ready for a big board design running a lot of parameter sweeps etc, my seat spends a lot of its time idle.
@gsuberland fwiw, the guide doesn't use FreeCAD as far as I could see - all the geometry is programmatically generated.
@miek @gsuberland yeah which i found completely unusable, my attempts to convert kicad to hyperlynx files and import them into openems ended... poorly.
that is IMO the single biggest thing holding back openems. It needs a nice easy to use frontend for setting up simulations with no code.
@gsuberland @azonenberg which guide is that?