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On to the ZBT SRAM! The die is a bit dirty but it's plenty clean enough for an overview.

The array is logically 256K rows x 18 bits. Physically, it appears to consist of a 2x2 tile of 64Kx18 SRAM arrays, with horizontal bus at the spine of each array and then vertical down the center of the chip,

Each of the arrays appears to consist of 16 smaller blocks with a... power? ground? line on top metal at the center of each. So these smaller blocks are 4K x 18.

And it looks like the blocks have 4-way horizontal symmetry within them, so they might be physically 1K x 72 with a 4-way column mux? We'll know more when I delayer.