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in order to single-step on this goddamn core, you have to program the two breakpoint/watchpoint units in tandem

the second one is used to match on only the address of the current instruction

and the first one is used to construct a NOT gate appended to the output of the second one

it took me like 20 minutes to figure out how to implement this, _and i write RTL professionally_

imagine being a developer with no RTL background or something :)

@whitequark what the fuck

is ARM9TDMI / ARM9E equally as bad? those are the cores we've actually used debug on, and we had always assumed that it should all "just work"

@r ARM9 is much, _much_ worse

@whitequark (what the fuck)^2

how did any embedded devs get anything done from ~1990-2010?

... is this why tools from that era were so secretive and expensive? and why so many devs from that era are so gatekeep-y and partake in so many intoxicants?

@r @whitequark have you looked at the PIC debug interface

@r @whitequark hell, even MIPS EJTAG is at least somewhat cursed

@azonenberg @r *somewhat*?!

i only know how to do debug entry on EJTAG 1.x/2.0 because of someone called "HairyDairyMaid a.k.a. lightbulb" which published the only copy of the code that use DMAAcc to enable PrAcc on those cores using undocumented flags

@azonenberg yeah EJTAG 3 is mostly fine, you just use PrAcc and it works

@azonenberg easier than ARM even

@whitequark I found ADIv5 easier to work with than EJTAG 3 but that may have been because it was several years down the road and I was more experienced with embedded bus architectures etc by that point

@azonenberg ADIv5 is somewhat overengineered, and EJTAG 3 is somewhat under-engineered, but I'd say that once you understand how a CPU works inside out, ADIv5 is just more busywork (at the benefit of being less annoying in corner cases)