Is there any way, in Vivado, to do "ex post facto timing analysis"?
In other words, can I take a post P&R design, write a new timing constraint, and (without attempting to change the existing design to meet it) get a timing report with the new constraint applied so I can see how far off I had been?
(the use case is troubleshooting weird malfunctions that you suspect are a missing constraint: if you add the new constraint ex post facto and see a failure on the exact signal that's acting funny, you can strongly suspect that you've found the problem that a reimplementation will hopefully fix. If it didn't fail, the problem lies elsewhere)
@azonenberg yes, just use SDC commands as normal and then rerun a timing report